Signal Integrity is Critical in High-Density Backplanes

As more performance is increasingly required of backplanes, the more critical the design.

Blog Post

As a signal travels across a network, it focuses only on what it sees in its path. And increases in data rates over the past few decades have made this path a bit more clouded.  System infrastructure needs to accommodate this increase through better bandwidth management, better system interoperability and higher data throughput. This is no short order.

Many of the challenges are being handled in the backplane, which manages much of the interconnect between various circuit boards or cards across a system. By cramming more electrical connections into the same footprint, high-density backplanes seem to invite signal integrity (SI) issues, making some embedded designers skeptical about how to best move this influx of data within their applications.  Here, we explore what influences signal integrity across a high density, high speed backplane.  

Signal Integrity Analysis Considerations

Signal integrity typically looks at the same parameters of backplane channels – insertion loss, return loss, operating margin, crosstalk, etc. – irrespective of the building blocks of the channel, how the system is architected or the intended data rates. The acceptable limits of these parameters are what vary, depending on the protocol/data rate. 

Co-design, or cooperation with your system manufacturing partner, at the layout stage is an important aspect of engineering a reliable embedded system.  Developing the building blocks of a system in parallel can reduce signal integrity issues, yielding better return loss and, more importantly, much better insertion loss.
It is essential that the data provided by both connector manufacturers and PCB manufacturers be first vetted for, then incorporated into, the analysis performed. For instance, this data is critical to the optimization and analysis of the PCB stackup and trace geometry parameters.  (Figure 1)

Figure 1: Signal Integrity Eye Diagram

Figure 1:
Figure 1: Channel performance is dependent on minimizing crosstalk across the connector.

As data rate increases, the type of weave used on the layers that carry high-speed signals is a critical consideration. With the advent of protocols that require lower intra and inter-pair skew, fiber weave induced skew may make or break the performance of some of the longer links in a system. Careful consideration has to be given to the compromise between a spread weave choice and the resin content for a given laminate material. The long-held assumption that the dielectric material surrounding the traces in the backplane or daughtercard PCBs is almost homogenous and isotropic in all directions is not only demonstrably false, but dangerous to make for high data rates transmission channels.

SI Simulation Considerations

Simulation at the pre-layout and post-layout stage is a necessary step, but without using validated models your simulations will only be as good as the assumptions built into those models. Vetting S-parameter models for passivity and causality as well as verifying the validity of a particular laminate material’s properties are just two examples.

While one would be tempted to consider simpler and oftentimes cheaper solutions for SI, one must be aware that – as is the case with everything else in life – you get what you pay for. And not all SI simulation and measurement tools are created equal.  “Half baked” solutions may get it right sometimes (even a broken clock is right twice a day) but investing diligently in proven simulation tools, test equipment, calibration and de-embedding techniques goes a long way to achieving good correlation between simulations and measurements, which is key to a successful approach to SI.

To truly test for signal integrity, it’s important to go beyond the scope of the application and account for worst-case scenarios to ensure your system, and your signals, will hold up under all circumstances.  Developing rules to test signal integrity only up to some artificial limits of the application will not give you an accurate picture of the system’s true limitations. One needs to account for a worst-case “margin” - this ‘margin’ allows for spikes in data transfer, higher than normal system loads, and less optimal designs of other components in the system (plug-in modules, mezzanine cards, power supplies, etc)

To properly model the signal path, the mated connector interface absolutely is an important consideration in the performance of a backplane assembly. The signal budget is affected by the plug-in cards that mate to the backplane, the backplane itself and the connectors used as interfaces between the plug-in cards and backplane. Moreover, it’s not only the electro-mechanical properties of these mated connector interfaces that affect the signal budget, but also the footprints used for these connectors, both on the plug-in cards and on the backplane (things like pad and anti-pad size, trace routing geometry in the area where it connects to the footprints, etc). (Figure 2)

Figure 2: Signal Integrity Charts VPX

Signal Integrity for VPX backplanes
Figure 2: Physical aspects of the signal path, such as the shape of the anti-pads, can impact signal integrity.


Ensuring Reliable Communications

At the end of the day, a backplane needs to go beyond merely meeting the signal budget allocated to it, even within the slightest margin. One must approach even individual subcomponents design with a holistic methodology. A poor (or marginally good) launch from a plug-in module into a backplane will only get worse – the backplane being a passive element of an end-to-end channel, it cannot improve the signal quality, since it will add loss (different kinds of loss too). Similarly, a backplane design with poor margins may actually result in a system failing. Make sure you have simulated, reviewed and properly measured (and post-processed) all the signal integrity parameters of relevance to your system to ensure reliable data transfer throughout your entire system.

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