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Compliant to PICMG 3.0 Rev 3.0 specifi cation
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Designed to meet 40Gbps ( 4 x 10G ports) data rates
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Based on design principles of IEEE 802.3ba-2010, 10GBASE-KR, and
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Nelco 4000 13-SI high grade laminate material
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Extensive pre-layout and post-layout simulation studies
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Backdrilled to minimize stub refl ections
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Very low insertion loss deviation (ILD)
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Dual shelf managers in slot 0, radial IPMB/I2C implementation
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Up to 400W/slot 48VDC distribution to each slot
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18 layer stripline design
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Test reports available upon request
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Accessories
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Datasheet/Brochure
More Info/Accessories
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